1. Field of the Invention
The present invention relates to a sampling clock generator circuit and a data receiver using the same circuit for use in a transmission system in which data is serially transmitted in units of n data at a frequency, which is n times a frequency of a transmitting clock signal, on a transmitting side, and converted into parallel data by using n sampling clock pulses on a receiving side as a receiving data, where n is an integer equal to or larger than 2, and a data receiving device using the same sampling clock generator circuit. In particular, the present invention relates to a sampling clock generator for generating a sampling clock signal with which a data sampling miss due to jitter of the external clock can be prevented, and a data receiving device using the sampling clock generator circuit.
2. Prior Art
It has been usual that, when data is transmitted from a personal computer to a peripheral unit, the data is serially transmitted together with a clock signal at high speed. In the serial data transmission system, a transmitting side transmits data serially in units of n data at a frequency, which is n times that of the clock CLK or with a period, which is one n-th of a period of the clock signal on the transmitting side, and a receiving side receives the clock signal having period n times that of the data as an external clock (a transmitting clock signal) together with the data and generates a sampling clock pulses the number of which is n times that of the clock signal on the transmitting side to convert the serial data transmitted in units of n data into a parallel data in units of n data on the basis of the n sampling clock pulses. Incidentally, n is an integer equal to or larger than 2.
A high speed transmission system of this kind is used in a data transmission from a personal computer, for example, to a color printer or a color liquid crystal display, a transmission within a digital TV or a set top box, etc., for example, and a data transmission in various communication equipments or in peripheral equipments of a computer. In order to receive the transmitted external clock CLK and output n data in parallel on the receiving side, the data receiving side generates sampling clock signal having frequency, which is n times that of the external clock CLK, by PLL control on the basis of the external clock CLK. Therefore, a sampling clock generator circuit of PLL control type is provided on the receiving side.
In such case, in order to restrict skew or jitter of the data and the clock during transmission thereof as small as possible, the sampling clock signal CLK having frequency, which is n times that of the external clock CLK, and generated in the receiving side is not obtained directly from an oscillator circuit oscillating at that frequency. That is, n clock pulses CK each having a period T, which is the same as the period T of the external clock CLK, and having phases mutually deviated are generated such that sampling clock pulses CK are located in centers of sub periods T/n obtained by dividing the period T of the external clock signal CLK by n. In other words, the sampling clock generator circuit generates n clocks CK including a first one of them having phase deviated from the data period T by T/2n and a second and subsequent clocks CK having phases deviated from directly preceding clocks by +T/n, respectively, and the rising edges of the n clock pulses CK are used as a sampling clock signal having frequency n times that of the external clock CLK. Therefore, the high frequency sampling clock signal can be obtained with precise timing on the receiving side.
Similarly, the transmission of the external clock signal CLK and the transmission of the data are performed simultaneously by transmitting each of them as positive and negative phase signal data through two lines having phase difference of 180°. In order to achieve this transmission, LVDS (Low Voltage Differential Signalling) system is used, in which signals having two phases are transmitted by a differentially operating transmitting/receiving buffer circuit.
A digital color liquid crystal display device is an example, which uses this system. In the digital liquid crystal display device, data is serially transmitted in units of 7 (n=7) data at a speed 7 (n=7) times a transmission speed of the external clock signal CLK transmitted from the computer and the data thus transmitted is outputted in parallel on the receiving side.
The sampling clock generator circuit for generating a sampling clock signal having frequency n times that of the external clock signal CLK on the receiving side in this case takes in the form of a PLL circuit utilizing a ring oscillator as a VCO (voltage controlled oscillator) as shown in FIG. 4. Outputs of n stages (when n is an even integer, n+1 stages) of the ring oscillator are derived as the sampling clocks.
In concrete, the sampling clock generator circuit 1 in the form of the PLL control circuit includes a phase comparator 2, a charge pump circuit 3, a low-pass filter (LPF) 4 and an ring oscillator 5 having series-connected 7 inverters, as shown in FIG. 4. The charge pump circuit 3 receives the output of the phase comparator 2 and an output current of the charge pump circuit 3 is inputted to the low-pass filter (LPF) 4.
In the sampling clock generator circuit 1 using the ring oscillator 5 as the VCO, an output voltage of the low-pass filter 4 for generating an oscillation control voltage is inputted to a voltage follower and an output of the voltage follower is supplied to a power source line for the odd number of inverters of the ring oscillator to drive them. An output of the inverter in the last stage of the ring oscillator is fedback to an input of the inverter in the first stage. Thus, the operating currents of the respective inverters are controlled according to the output voltage of the LPF 4 to control the oscillation frequency of the ring oscillator.
The external clock signal CLK, which is transmitted from the computer as the transmitting side through a transmission circuit 9 and has a period T, is inputted to the phase comparator 2 and n (n=7) clock pulses CK are derived from the inverters in the odd numbered stage of the ring oscillator 5 in synchronism with the external clock signal CLK. Therefore, the ring oscillator 5 is composed of series-connected 7 inverters.
The n (=7) clock pulses CK obtained by the ring oscillator 5 are sent to a serial/parallel converter circuit 6 as a sampling clock to sample three data corresponding to R, G and B, which are supplied serially from the data receiving circuit 7 to the serial/parallel converter circuit 6. The serial/parallel converter circuit 6 converts the R, G and B data into a parallel data in units of n (=7) data at a rate, which is n (=7) times the data transmission rate. The parallel data is supplied to a controller 8.
Incidentally, a reference numeral 10a depicts data lines between the transmitting circuit 9 on the computer side and the receiving circuit 7 on the liquid crystal display side and a reference numeral 10b depicts the transmission lines for the external clock signal CLK between the transmitting circuit 9 on the computer side and the receiving circuit 7 on the liquid crystal display side. The transmission and the receiving in this case is performed by transmission and receiving of the respective data and the external clock signal CLK using the LVDS system through two signals having phase difference of 180° obtained by a differential amplifier as a driver.
The sampling clock pulses CK outputted from the ring oscillator 5 are derived from the odd-numbered inverter stages and the phase of the sampling clock pulse CK of the first inverter stage is shifted from the external clock signal CLK by T/2n (2n=14), where T is the period of the external clock signal CLK, and the phases of the sampling clock pulses CK from the subsequent odd-numbered inverter stages are shifted by +T/n (n=7) from immediately preceding inverter stages, respectively, as shown in FIG. 5. In a case, the sampling clock pulse CK of the second inverter stage becomes the sampling clock pulse CK of the ninth inverter stage, the sampling clock pulse CK of the forth inverter stage becomes the sampling clock pulse CK of the eleven inverter stage and the sampling clock pulse CK of the sixth inverter stage becomes the sampling clock pulse CK of the thirteenth inverter stage.
The rising edges of these clocks CK become sampling timing of the data. In this manner, when data is to be transmitted at a frequency n times that of the external clock signal CLK, rising or falling edges of the n clock pulses CK are used as sampling clocks having frequency equivalent to n times that of the received external clock signal CLK.
In a case where XGA (1024×768) display is performed by the liquid crystal display device, however, the period of the external clock signal CLK is limited to the order of 15.38 nano sec (≈65 MHz) and the period of data transmitted at a rate n times that of the external clock signal CLK is as short as 2.20 nano sec (≈455 MHz). Therefore, if there is jitter in the external clock signal CLK transmitted through a cable, a deviation in phase between the transmitted data and the transmitted clock becomes large, so that a period in which the rising and falling of the data becomes uncertain is shifted, resulting in that a range in which data sampling can be done becomes 1 nano second or shorter. Therefore, even when sampling clocks at a speed n times that of the external clock signal CLK can be generated by PLL control, there is a problem that a highly precise data receiving can not be done.
An example of the timing problem due to jitter is shown in an ellipsoidal area in FIG. 5. As shown in FIG. 5, the rising edges of the respective clocks CK, which are PLL-controlled, do not correspond to the rising edge of the external clock signal CLK. Therefore, if the external clock signal CLK is delayed, the rising edges of the clocks CK are advanced with respect to the rising edge of the external clock signal CLK, so that it becomes impossible to sample the data, which is synchronized with the external clock signal CLK and has a frequency n times that of the external clock signal CLK, that is, a period of one n-th of the period of the external clock signal CLK.